PURPOSE: To improve the access speed of a main storage while securing the universal applicability of the storage by generating the address latch signals synchronous with a clock signal and distributing these address latch signals to each bank during the generation of a control signal or a display signal.
CONSTITUTION: A microprocessor 10 generates a control signal which continues for at least a period of cycles equivalent to the address first-out frequency of a pipeline right after the start of a pipeline operation. At the same time, a display signal generating circuit 24 produces a display signal to show the end of a data access to a bank. Then the address latch signals synchronous with a clock signal are generated during the generation of the control signal or the display signal. These address latch signals are distributed to the banks respectively. Thus the access speed of a main storage is improved together with the universal applicability of the storage maintained.