Data write control device

Abstract

PURPOSE: To make it possible to simultaneously write the same data in plural data transmitting/receiving means and to shorten time required writing by allocating a common address to the plural data transmitting/receiving means. CONSTITUTION: Respective peripheral apparatuses 12a to 12c respectively have plural writing addresses and these addresses are common in respective apparatuses 12a to 12c. When a CPU 10 generates an address, a writing address decoder 22a applies a write instruction to the apparatus 12a and a write address decoder 22b applies a write instruction to the apparatus 12b, so that the same data can be written from a data bus 14 to the apparatuses 12a, 12b. In the case of reading out data, the data can be read out from respective peripheral apparatuses by generating an address from the CPU 10. COPYRIGHT: (C)1992,JPO&Japio

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    JP-2007102467-AApril 19, 2007Denso Corp, 株式会社デンソーマイクロコンピュータ