Delay analyzing system

Abstract

PURPOSE: To enable a delay analysis at a high speed even in a logical circuit of the large size of combination type by replacing the logical circuit of a combination type with a delay calculating circuit and an event generating circuit which are capable of being directly executed, and operating the delay analysis at the high speed. CONSTITUTION: Each logical gate of the logical circuit to be analyzed is replaced with a delay calculating circuit 3 and an event generating circuit 4. Then, an entire controlling circuit applies the change of an input time to the input side of the delay calculating circuit 3, and a delay value is taken out from an output side. Moreover, the starting command of a pass search is inputted from the output side of the event generating circuit 4, an event generating element 6 of the event generating circuit 4 inputs input selecting signals as needed to a delay calculating element 5 corresponding to the delay calculating circuit 3, so that the pass which fulfills a condition can be searched by repeating the delay calculating request of the pass. Thus, the delay analysis can be attained at the high speed in the logical circuit of the large size of the combination type. COPYRIGHT: (C)1992,JPO&Japio

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    JP-H0896016-AApril 12, 1996Nec Corp, 日本電気株式会社Logical simulation method